CpldProgramming

Pretty much the first thing you want to do after confirming that your board powers up correctly and that the BF532 can be probed using JTAG is program the CPLD. The CPLD provides the glue logic to the SPI and parallel flash chips so you can't flash uboot or uclinux onto the BF1 board without it.

1. Download the BF1_CPLD_ISE.zip from the [[][BF1 site]]
2. Download and istall the ISE from xilinx.com
   1. Create a new project
   2. Add the bf1_cpld.v file as a new source file
   3. Build the project - this should create a .JED file
3. Connect your Jtag dongle to the BFJTAG2 header (add pinout here)
4. Open the .JED file and program the CPLD with that
5. Verify that the chip was programmed
   • Fire up jtagtools
   • Setup for some playing around

     • cable parallel 0x378 DLC5
       detect
       initbus bf532_bf1
       

   • Get out the scope or a multimeter, get a good ground and pin 19 of the CPLD (or pin 7 of the SPI flash)
     • Initially the pin your are probing is pulled high (3.3V)
   • Execute spidetectflash 0 in jtagtools
     • The probed pin should drop to 0V for a split second (it is the SPI chip select pin)
     • You can also probe pin 18 of the CPLD - this is PF2 from the blackfin and PF2 == SPI_FLASH_CS
       • If PF2 goes low and PSI_FLASH_CS does not then the CPLD is not programmed correctly

-- ChristopherPepe - 03 Jan 2007